1. Field of the Invention
The present invention relates to the field of high-density electrical connectors, and more particularly, to the class of connectors that provides electrical contact and conduction at one surface by means of surface contact or direct compression.
Whereas patent application Ser. No. 08/752,713 is directed to the placement of a formed loop of wire within an insulating sleeve which is then inserted into an electrically conductive or magnetically permeable housing, the present invention directs the placement of the wire loop directly into the housing without a sleeve. This method uses the existing wire insulation to isolate the inner electrical conductive wire from an electrically conductive housing, or alternatively, have the insulation removed from the entire wire loop or wire segments and placing the wire loop/segments into a non-conductive housing. Each connector can be interconnected with single wire or twisted with another wire using methods described in my U.S. Pat. No. 5,042,146.
2. Description of the Related Art
Because present trends in designing microelectronic devices and circuits are toward increased miniaturization, higher component density and greater number of component leads per piece-part, there is a corresponding need for connectors that can be configured in high-density, large-number arrays. Techniques known in the art for providing high-density interconnections between a monolithic integrated circuit (IC) or multi-chip module (MCM) and a printed wiring board (PWB) include the use of quad flat-packs (QFP) which surrounds an IC or MCM on four sides with wire/lead interconnections or the use of leadless chip-carrier (LCC) which surrounds the four outer sides of an IC/MCM with vertical, flush, interconnecting leads. High-density interconnection techniques wherein connections are arranged in a two-dimensional array located under or near the substrate of an IC/MCM or the base of a PWB include the use of land grid arrays (LGA's), ball grid arrays (BGA's), and pin grid arrays (PGA's). Such arrays can provide short interconnections while permitting a high density of connections. LGA's and BGA's have become popular in part because production equipment used to mount and solder surface-mount devices onto circuit boards can be easily adapted. This ease of manufacture is enhanced by the tendency of array pads on which components will be soldered to self-align by the effects of surface tension caused by the molten solder.
Chip-scale packaging (CSP) is another emerging technique for interfacing an IC to a substrate/circuit board. Still in its infancy, this technology has the potential to provide direct connections between package or circuit board input/output (I/O) pads to IC die or MCM substrates. Typically a CSP package occupies an area that is 20% larger than the size of the die.
Because circuit miniaturization and high-density components entail ever-increasing signal speeds and input/output rates, newly developed devices increasingly require interconnections that can provide adequate shielding to pass low-noise signals or maintain a proper and uniform characteristic impedance to pass signals with fast edges (.DELTA.v/.DELTA.t) or any signal having a high-frequency harmonic content. In PWB design, characteristic impedance control has been achieved by using strip-line or micro-strip techniques which requires careful control of the size, position and spacing of circuit traces within a dielectric that is spaced away from a ground or reference plane. However, applying strip-line or micro-strip connections to the inner pads of a high-density PWB becomes more difficult as circuit density increases. Also, more layers and increased manufacturing must be used when a device requires numerous, homogenous, shielded, impedance-controlled interconnections. Increased circuit density requires more connections per unit area, especially if numerous ground planes (as required when using micro-strips or strip-lines) are utilized.
U.S. Pat. No. 4,679,321 to J. P. Plonski describes an interconnection board for high frequency signals wherein connectors are in close proximity. The board is constructed having one side provided with a ground plane and the other side provided with terminal pads and interconnection conductors. Holes are drilled through the board at the terminal points. An end of the center conductor of a coaxial cable, stripped of insulation, is inserted through each hole while the conductive shield remains on the other side of the board. Each bare-wire conductor is connected to a pad and the conductors are scribed and bonded into place. The shields can be interconnected by applying a plated copper layer or a conductive encapsulating layer or by reflow soldering.
U.S. Pat. No. 3,114,194 to W. Lohs describes a method of wiring an electrical circuit upon an insulating plate provided with a plurality of holes, whereby wire lengths are kept as short as possible and wires can be crossed. Insulated wire is drawn through a hole in the plate and a loop formed from the wire projecting through the hole. The loop is then crushed to simultaneously anchor the loop into the hole and expose a conductive area.
My prior patent, U.S. Pat. No. 5,042,146 ("146"), discloses a process and apparatus for forming double-helix contact receptacles directly from insulated wire, for interconnecting components independent of printed circuitry. Some of the apparatus disclosed therein, specifically the wire processing mechanism including cutting, stripping, and handling assemblies, is readily adaptable to the present invention which, like the "146" patent, is capable of handling and incorporating both single and twisted-pair insulated wire. Alternatively, coaxial cable can be used with the center conductor in lieu of a single conductor, provided the shield does not contact the center conductor.
My prior patent, U.S. Pat. No. 5,250,759 ("759") entitled "Surface Mount Component Pads", which is incorporated herein by reference in its entirety, discloses a method to form pads for surface-mount electronic components by inserting a stripped portion of insulated wire into an elongated rectangular opening, and anchoring the formed elongated U-shaped loop into place with epoxy or a plug. Although the pads disclosed in the '759 patent can be used with area arrays, their elongated pads will not mesh well geometrically with the square pads normally used in arrays. In addition, due to their shape, elongated pads cannot be disposed sufficiently dense in planar arrays to meet the close proximity requirements of LGA's or BGA's.